1. Technical Field
The present invention relates to a method and stricture for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving system resistance and characteristic impedance requirements.
2. Related Art
Semiconductor chip size continues to decrease, with an attendant increase in component density. The electrical signals which provide communication between chips, via electrically conductive wires or lines, are characterized by increasing operational frequencies. Semiconductor chips mounted on a printed circuit board (“PCB”) are subjected to detrimental effects caused by the inherent resistance of the PCB wiring which interconnects the semiconductor chips. A typical high performance printed circuit board has traditionally not been able to use wiring densities beyond a certain point due to limitations imposed by the DC resistance maximum in interchip wiring networks. Similarly, higher frequency signals also demand wide lines as a means to minimize “skin effect” losses in long lines. Unfortunately, it is problematic to generate dense wiring between a plurality of semiconductor chips on a PCB or chip carrier.
The usual solution is to use the typical geometry of wide wire lines and appropriate dielectric layer thicknesses to produce a 50 ohm transmission line characteristic impedance (Z0), and achieve a wiring network with a single wiring layer pair that uses only lower capacitance buried vias and a limited number of higher capacitance plated through hole vias. The result of this approach is that more wiring layers are required, and with a correspondingly thicker printed circuit board structure resulting. Future projections of component input/output (I/O) counts (e.g., approaching 4000 I/0 counts with an I/O pitch of 0.8 mm) require a solution other than this usual practice.
An alternative is to use fine wire lines that widen when sufficient space is available. However, these wire lines do not maintain the necessary transmission line characteristic impedance (Z0) in all areas. These wire lines also have circuitization yield implications that make them unattractive in most printed circuit board applications.
Thus, there is a need for a method and structure that implements dense wiring, in printed circuit board or chip carrier applications, and which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements.